1. Field of the Invention
The present invention relates generally to a DRAM circuit and an operating method thereof, and more particularly, to an arrangement of a sense amplifier and a peripheral circuit thereof in a DRAM array, and an operation of the sense amplifier.
2. Background of the Invention
In a DRAM, each space between bit lines is narrowed with progress of a process technology, so that a problem of increasing an interference noise occurs. The interference noise referred to here means a noise resulting from a coupling capacitance between the bit lines. This interference noise can be classified into an interference noise between the bit lines connected to one sense amplifier and an interference noise between the adjacent bit lines connected to different sense amplifiers.
As a conventional technique to overcome the problem of the interference noise, there is a twisted bit line system (hereinafter, referred to as the TBL system). Examples of known documents regarding the TBL system include Japanese Patent Application Laid-open Nos. 183489/1990, 94569/1992, 94597/1995 and 168300/2001, the disclosure of which are incorporated by reference herein. FIG. 1 is a conceptual view of the TBL system for use in an embedded DRAM (hereinafter, referred to as the eDRAM) which is a product of IBM Corporation (known document: ISSCC 2002 Digest of Technical Papers, pp. 156–157, the disclosures of which is incorporated by reference herein). In FIG. 1, bit line pairs (BL0t, BL0c) to (BL3t, BL3c) are connected to sense amplifiers (SA) and bit switches (BSW) while they cross each other on the way. This cross of the bit lines reduces the interference noise between the bit lines (e.g., BL0c and BL1t) connected to the adjacent different sense amplifiers. That is because a space between the bit lines (for example, BL0c and BL1t) changes (broadly or narrowly) from the position of the cross.
However, in the system of FIG. 1, there is a problem that the interference noise between the bit lines connected to the one sense amplifier is not reduced. That is because a space between the bit lines (e.g., BL0t and BL0c) does not change from the position of the cross. Furthermore, as viewed in a vertical direction, the bit lines cross at three portions, and hence, there is a problem that its cross area prevents the realization of a high density, because the connection of a memory cell is impossible at the cross of the bit lines. An area loss at one cross corresponds to about two cells. Owing to the three bit line crosses, there is a problem that four reference word lines (RFWL0–4) is necessary for a read operation and the area for these word lines also prevents the realization of the high density. In the DRAM of, for example, a (½) Vdd pre-charge system which does not need the reference word lines (RFWL0–4), there does not rise any problem regarding the reference word lines (RFWL0–4).
Another prior art which solves the problems of interference noise includes a multiple twisted bit line method (hereinafter referred to as an MTBL method). FIG. 2 shows an example of the MTBL method (known document: IEEE JSSC vol 34, No 6, pp. 856–865 June 1999, the disclosure of which is incorporated by reference herein). In the method of FIG. 2, bit lines of a bit line pair (BL1t, BL1c) cross at one place on the way, and from the crossing, a space between the bit lines is wider. The same is seen in a bit line pair (BL3t, BL3c). Bit lines of a bit line pair (BL0t, BL0c) do not cross, and a space between the bit lines is wider on the way. The same is seen in a bit line pair (BL2t, BL2c). Therefore, in the MTBL method of FIG. 2, both in the bit lines connected to the same sense amplifier (e.g., BL1t, BL1c) and in the bit lines among adjacent bit lines connected to the different sense amplifiers (e.g., BL0c, BL1c), the space between the bit lines changes (widens or narrows) before and after the cross. Thus, the interference noise between any adjacent bit lines is decreased. In this regard, the MTBL method of FIG. 2 is superior to the TBL method of FIG. 1.
Furthermore, the bit lines cross at one place in the method of FIG. 2. In addition, only two reference word lines (RFWL0, 1) are sufficient. Accordingly, the MTBL method of FIG. 2 has an effect of area improvement, as compared with the TBL method of FIG. 1.
However, in the MTBL method of FIG. 2, the sense amplifiers (SA) and the bit switches (BSW) are needed on both sides of the array, which causes a loss of area. For example, the eDRAM is configured by cumulating the constitution of FIG. 2 as a macro, as shown in FIG. 3. Therefore, as shown in FIG. 4, duplication of the sense amplifiers (SA) and the bit switches (BSW) is caused above and below the arrays and takes up the area for them, thus causing a problem of preventing high density. For example, in the eDRAM of 16 Mb shown in FIG. 3 in which 16 DRAMs of 1 Mb are piled up, an area of about 525 micrometers, which is fifteen times as high as the 35-micrometer sense amplifiers (SA) and the bit switches (BSW), is unnecessarily used.
The present invention has been attained to solve the problems of the prior art described above, and its object is to provide a DRAM which reduces interference noise between bit lines.
Furthermore, an object of the present invention is to apply a high-density DRAM which reduces interference noise between bit lines.
Still further, an object of the present invention is to provide a high-density DRAM in an MTBL method which reduces interference noise between bit lines.